1. Field of the Invention
The present invention relates to a sigma-delta modulator and method thereof, and more particularly, to a sigma-delta modulator and method for controlling an output rate according to an amplitude of input signals.
2. Description of the Prior Art
Sigma-delta modulators are already commonly applied to analog-to-digital converters (ADC) and digital-to-analog converters (DAC) because the sigma-delta modulators have the capability of noise shaping to reduce quantization noise within signal bandwidths and to further increase the signal to noise ratio (SNR). However, due to over-sampling inherent in a sigma-delta modulator, its output rate is proportional to its capability of noise-suppression. Therefore, this higher output rate reduces the overall efficiency and may restrict applications of sigma-delta modulators.
In order to reduce the output rate of the sigma-delta modulator, several methods have been proposed, such as those disclosed in the U.S. Pat. No. 5,815,102 and 6,924,757, and the reference document “Digital power amplification using sigma-delta modulation and bit flipping” proposed in J.AES, vol. 45, no. 6, June 1997. In the U.S. Pat. No. 5,815,102, Melanson reduces the output rate of the sigma-delta modulator by using PDM-to-PWM conversion. However, this method is merely suitable for digital data, and the PDM-to-PWM conversion induces extra noise and thus needs a special correction mechanism. In U.S. Pat. No. 6,924,757, Adams adjusts the threshold values of a quantizer by adjusting the hysteresis parameters, and thereby the output rate of the sigma-delta modulator can be reduced. But this method is merely suitable for a one-bit quantizer only. For multi-bit applications, this method may become extremely complicated or may not work. In the reference document proposed in J.AES, a bit-flipping technique is used for reducing the output rate via changing the output code of the sigma-delta modulator. This method is applicable in a one bit sigma-delta modulator only.